Efficient AES-XTS Pipelined Implementation on FPGA
DOI:
https://doi.org/10.33317/ssurj.56Keywords:
Cryptography, XTS-AES, FPGA.Abstract
In past years, it has been considered that only data communicated via networks need to be secured. This paradigm
now shifted towards securing data at rest. With its increasing significance, IEEE has introduced a mode of Advanced
Encryption Standard (AES) named as XTS-AES. Few of its implementations exist. This paper presents a high throughput and highly efficient fully unrolled pipelined design of AES-XTS on FPGA. The proposed implementation incorporates only one AES core for both tweak value encryption as well as data encryption. Further our proposed design calculates tweak value in parallel to data encryption/decryption process. The results have achieved a throughput of 35.8 Gbps with an efficiency of 8.4 Mbps/slice. This design offers the best result for Throughput/Area that is 4.641 Mbps/area.
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